The Apsara Algorithm Is an Input-queued Switch Scheduler That Uses Limited Parallelism to Find a Matching in a Single

bandwidth has led to increasingly higherspeed links and caused an associated demand for routers with a high aggregate switching capacity. At the highest speeds, input-queued (IQ) switches have become the architecture of choice, mainly because the memory bandwidth of their packet buffers is very low compared to that of output-queued and shared-memory architectures. To perform well, however, an N × N IQ switch requires a good packet scheduling algorithm to determine which inputs to connect with which outputs in each time slot. The maximum-weight matching (MWM) algorithm finds, from among N ! possible matchings, the matching with the highest weight. Here, the weight of the edge connecting input i to output j can either be the number of packets queued at input i for output j or the age of the oldest packet at input i for output j. The MWM algorithm is known to provide a 100 percent throughput1-3 as long as no input or output is over subscribed. It achieves a low average delay by keeping queue lengths short. However, MWM is complex to implement: It needs O(N 3) iterations in the worst case and does not lend itself to an easy pipelined implementation. These implementation obstacles have motivated the proposal of several scheduling algorithms for high-speed switches, such as iterative SLIP (iSLIP),4 iterative longest-queue first (iLQF),5 reservation with preemption and acknowledgment (RPA),6 and matrix unit cell scheduler (MUCS).7 However, these algorithms perform poorly compared to MWM when the input traffic is nonuniform: They induce large delays, and their throughput can be less than 100 percent. Thus, although the other algorithms mentioned aim to solve implementation problems, their performance is poor. This situation raises the question, is it possible for an algorithm to compete with MWM’s performance and yet be simple to implement? If yes, what feature of the problem remains to be exploited? The answer lies in recognizing two features of the high-speed switch-scheduling problem: